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Professor Jari Nurmi

      Jari Nurmi
Doctor of Science in Technology, Professor

Field of Expertise

Embedded RISC and DSP Processor Architecture, Network-on-Chip, Embedded System-on-Chip Design, Embedded Manycore Computing Platforms, Signal Processing and Digital Communication Circuits, Positioning Receivers, Software-Defined Radio.

See the biography for further information.

Mailing (visiting) address

Tampere University of Technology
Department of Electronics and Communications Engineering
P.O. Box 553
FIN-33101 Tampere
(Korkeakoulunkatu 1 G 308)
(FIN-33720 Tampere)
FINLAND

Electrical media addresses

Phone +358 40 506 4460
Email jari dot nurmi at tut dot fi
URL http://www.cs.tut.fi/~nurmi/
LinkedIn https://fi.linkedin.com/in/jarinurmi

Some internal links

Books Edited

  • Jari Nurmi, Hannu Tenhunen, Jouni Isoaho, and Axel Jantsch (Eds.), Interconnect-Centric Design for Advanced SoC and NoC, Kluwer Academic Publishers, 2004, ISBN 1-4020-7835-8.
  • Jari Nurmi (Ed.), Processor Design: System-on-Chip Computing for ASICs and FPGAs, Springer, 2007, ISBN 978-1-4020-5529-4.
  • Jari Nurmi, Elena-Simona Lohan, Stephan Sand, and Heikki Hurskainen (Eds.), GALILEO Positioning Technology, Springer, 2014, ISBN 978-94-007-1829-6, Doi 10.1007/978-94-007-1830-2.
  • Jari Nurmi, Jouni Isoaho, Fabio Garzia, and Waqar Hussain (Eds.), Computing Platforms for Software-Defined Radio, Springer, 2016. (under construction)
  • Jari Nurmi, Elena-Simona Lohan, Gonzalo Seco-Granados, Henk Wymeersch, and Ossi Nykänen (Eds.), Multi-Technology Positioning, Springer, 2016. (under construction)
  • 17 conference proceedings by year 2016
  • Recent International Projects

  • SYSMODEL - System Level Modeling Environment for SMEs
  • GRAMMAR - Galileo Ready Advanced Mass Market Receiver
  • CRISP - Cutting Edge Reconfigurable ICs for Stream Processing
  • MULTI-POS - Multitechnology Positioning Professionals (ITN)
  • TETRACOM - Technology Transfer in Computing Systems
  • Recent Doctoral Theses Supervised

  • Waqar Hussain, 2014: Design and Development from Single Core Reconfigurable Accelerators to a Heterogeneous Accelerator-Rich Reconfigurable Platform
  • Sarang Thombre, 2014: Test Bench Solutions for Advanced GNSS Receivers: Implementation, Automation and Application
  • Omer Anjum, 2014: Software-Defined Radio: Challenges and Opportunities in Baseband Processing Architectures
  • Roberto Airoldi, 2013: Design and Implementation of Software Defined Radios on a Multi-Processor Architecture
  • Subayal Aftab Khan, 2012: System Level Performance Evaluation of Distributed Embedded Systems
  • Piia Saastamoinen, 2012: Program Code Compression on Single- and Multi-Core Systems
  • Sanna Määttä, 2011: Modeling Embedded Applications for On-Chip Multiprocessing Systems
  • Heikki Hurskainen, 2009: Research Tools and Architectural Considerations for Future GNSS Receivers
  • Fabio Garzia, 2009: From Run-Time Reconfigurable Coarse-Grain Arrays to Application-Specific Accelerator Design
  • Claudio Brunelli, 2008: Design of Hardware Accelerators for Embedded Multimedia Applications
  • Xin Wang, 2008: Designing Globally-Asynchronous Locally-Synchronous On-Chip Communication Networks
  • Yang Qu, 2007: System-level Design and Configuration Management for Run-time Reconfigurable Devices
  • Tapani Ahonen, 2006: Network-Based Single-Chip System Architectures
  • Heikki Kariniemi, 2006: On-Line Reconfigurable Extended Generalized Fat Tree Network-on-Chip for Multiprocessor System-on-Chip Circuits
  • Lasse Harju, 2006: Programmable Receiver Architectures for Multimode Mobile Terminals
  • Tapio Ristimäki, 2005: Reconfigurable IP Blocks: a MIMD Approach
  • David Sigüenza Tortosa, 2005: PROTEO: The Development of a Practical Network-on-Chip
  • Christian Panis, 2004: Scalable DSP Core Architecture Addressing Compiler Requirements
  • Mika Kuulusa, 2000: DSP Processor Core-Based Wireless System Design
  • All Doctoral, Licentiate and MSc Theses

  • List of theses
  • Conferences

  • IEEE NorCAS (in steering committee, general chair)
  • ICL-GNSS (in steering committee, chairman)
  • DASIP (in steering committee)
  • FPL (in steering committee)
  • Annual Tampere SoC Event (International Symposium on System-on-Chip) - history page
  • Thesis supervision

  • Get a supervisor for your MSc or PhD thesis
  • The research group working on:

    • Processor and co-processor architectures and design (e.g. Coffee RISC Core)
    • On-chip communication, Network-on-Chip, multi-processor SoC platforms (e.g. look at web page of Dr. Tapani Ahonen)
    • Communications and positioning receiver implementations, Software-Defined Radio, wireless positioning
    • Coarse-grained Reconfigurable Arrays (CGRAs)

    More on Research in Team Nurmi

  • Article about Team Nurmi, in TUT electronic staff magazine Kaapeli.
  • Article about conference organization, in TUT electronic staff magazine Kaapeli (in Finnish).
  • Article on positioning, in TUT electronic stakeholder magazine Rajapinta (in Finnish).
  • Some external links

    Tampere - The SoC City!

  • Tampere City
  • Tampere Hall
  • Tampere SoC Symposium Series
  • Weather in Tampere
  • Tampere University of Technology
  • Tampere University
  • Ilves
  • Tappara
  • Funding sources

  • TEKES (The Finnish Funding Agency for Technology and Innovations)
  • Academy of Finland
  • EU Seventh Framework Programme
  • ARTEMIS
  • European GNSS Agency

  • jari dot nurmi at tut dot fi