System on Chip Seminar 2001
Enabling Technologies for System-on-Chip Development
The Panel Discussion Summary
Chairman: Prof. Jari Nurmi, Tampere University of Technology Participants: Prof. Francky Catthoor, IMEC Prof. Keshab Parhi, University of Minnesota Prof. Vijay Madisetti, Georgia Tech Mr. Marcus Willems, Synopsys, Inc. Mr. Oz Levia, Improv Systems, Inc.
The panel session was initiated by each participant with a short presentation on a subject they considered important under the topic.
Vijay Madisetti talked about System-on-Chip (SoC) showstoppers, i.e., issues that slow down the large-scale breakthrough and distribution of SoC designs. He divided those into four categories: legal, business, technical, and competitive challenges. The main legislative obstacle for unrevealing SoC innovations is the intellectual property (IP) protection. Every company is worried about illegal copies and exploitation of their inventions. Highly restrictive license terms with considerable fees are applied for protection and profit. Business showstoppers include short time-to-market requirements, which often result in poor products. In addition, products come always a step behind the most novel technology: it is not possible to use the most advanced technology in the newest products since product development itself also takes time. The fact that there do not exist complete SoC design packages with perfect tools, models, and formalisms also slows down and complicates development. Competitive challenges, such as the stated time-to-market requirements, product completeness, and SoC support packages, delay development and new product releases. However, probably the most important problem is that technical and economical requirements are usually conflicting.
Francky Catthoor discussed the management of dynamic concurrent tasks in real-time multimedia systems. This is the key problem in future SoC design since applications are becoming more and more dynamic and concurrent. For example, an image that has its background and foreground on different layers needs more concurrent computation compared to traditional bitmap images. Catthoor divided the system-level design into three areas: algorithms, data structures, and platform constraints. Efficient algorithms are required for concurrency management and data structures for information management. The goal is to map dynamic and concurrent designs into multi-process systems. After finding a proper solution, it is possible to maximize quality and minimize power consumption. In addition to difficult design, highly dynamic behaviour makes the worst-case realization too costly.
Oz Levia tried to describe the crucial part of SoC design in his speech. He stated that it is often the one we do not have. Previously this has been a proper compiler, now it is the design methodology. A good methodology enables finding the best mapping between an application and a system. The lack of such a method implies slow design space exploration and hinders dynamic mapping. In addition, design tools have a great role in processing complex SoC designs. They are required for giving feedback on functionality, performance, efficiency, power consumption, and cost. After developing efficient tools, the heavy burden of the exploration and dynamic mapping can be shifted from the designer to automatic design tools.
Keshab Parhi’s introduction was about SoC challenges. Since the transistor counts in SoC designs are constantly increasing also the design challenges become more demanding. Currently, the SoC chips contain millions of transistors. Most difficulties are due to power consumption, integrating chips from different vendors, understanding how chips relate to the technology (e.g. power and performance), and software/hardware partitioning. According to Parhi, software and hardware are and will be equally important in SoC. Once again, developing efficient methodology and design tools is very important.
Markus Willems outlined the trends in SoC design. It was stated that the amount of software in SoC is going to grow quicker than the amount of hardware. It is also very important to develop efficient software/hardware co-design methodologies. Co-verification should be fast and it should be done in an early design phase. In order to enable easier design of larger systems, the abstraction level must be raised above the register transfer level (RTL). In addition, a straight path from the design to the implementation must be found. Higher abstraction and design reuse can be achieved with a standard description language and platform concept. Reuse alleviates the design of large systems and shortens the development time.
DiscussionThe discussion itself consisted of answering the questions from the audience and commenting the claims of the participants. The audience was mainly interested in the future of SoC design.
Trends in SoC
More clearance was inquired on the participants’ opinions about the trends in SoC design. It became clear that currently application specific integrated circuits (ASIC) are ahead reconfigurable logic in power consumption and performance and dynamically reconfigurable logic (DRL) is still too hard to coupe with. However, in the future ASICs are going to be out due to their lack of adaptability – especially for dynamic multimedia systems. Advanced DRL will replace ASICs in most applications and only very-large-volume products will utilize ASICs. However, DRL will not achieve this popularity as long as only fine-grained reconfigurable architectures, such as field programmable gate arrays (FPGA), are used. It was foreseen that the trend will be towards coarse-grained systems in which the connections between large functional blocks can be dynamically configured. It was also pointed out that there is very little difference between digital signal processors (DSP) and dynamic reconfiguration and predicted that the small gab will become even narrower. Once again, the shift from the current situation to large-scale utilization of DRL requires also considerable advances in design tool development.
The audience wondered how the physical limits of silicon, which soon will be reached, are dealt with. One obvious solution is to increase the level of parallelism instead of increasing the clock frequency. Pushing the clock only causes new problems as a form of power consumption and heat. Dynamical reconfiguration and proper chip partitioning should also alleviate the problem. Designers have to pay special attention to hierarchy and organization of subsystems in order to diminish communication problems. Furthermore, since memories consume most energy, they should be distributed and used as efficiently as possible. The physical limits will also cause new problems in place and route (P&R). However, it is up to designers how bad the problems get. By just increasing the clock frequency instead of utilizing parallelism, designing properly, and developing efficient algorithm we will definitely get in trouble.
The future of SoC development tools occupied the audience. It was claimed that efficient tools are only made for the tasks people are willing to pay for. High-level-language compilers have been poor since people are used to pay only a little for them. However, this claim was heavily criticized. Generally, it was estimated that design abstraction level as well as the operating level of the companies in the field is going to rise. For example, the companies currently producing logic synthesis tools are going to move higher in the stack and start developing design tools. A smooth design flow with proper tools from a high-level description to a final product has to be developed. This can only be achieved by seriously investing the design tool development.
The audience contradicted the possibility of utilizing parallelism. It was claimed that it is too difficult to take advantage of concurrency in large and complicated applications. The participants believed that the problems of parallelism will be gradually solved. Accepting that optimum may not be reached, careful design, and writing well-structured code can help. For example, if the code is written carefully, parallelism is visible and thus easily exploitable. In addition, it was argued that managing concurrency in embedded systems is often easier than in the general-purpose world (e.g. video codec vs. word processor). In some cases it is also possible to switch the utilized algorithm to a more suitable one for parallel processing. Real-time scheduling was also suggested as one solution but the panelists did not regard that as a very good solution.
As a conclusion of the discussion, it was stated that in the future dynamically configurable platforms will widely be utilized in SoC designs. Dedicated hardware will only be used in very-high-volume products. However, in order to enable this shift, advances in the technology as well as efficient development tools and methodologies are required.