System on Chip Seminar

SoC 1999

SoC 2000

SoC 2001

SoC 2002

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Designing Networks On Chip: solutions and challenges

Luca Benini

Interconnection network design is becoming one of the most critical issues in current SoC development flows. Commonly adopted architectures (such as shared busses), do not scale well as complexity and parallelism increases, therefore circuit designers and chip architects are actively investigating alternative and novel approaches for eliminating communication bottlenecks. The quest for higher communication performance, reliability and energy efficiency is determining a paradigm shift from a computation-centric to a communication-centric view of SoC architectures, centered on the concept of Network-on-Chip. In this talk, we survey various network-on-chip architectures in last-generation multiprocessors on a chip for DSP, multimedia, graphics and various embedded application domains. We critically analyze the state of the art to pinpoint open challenges and opportunities, and to provide general NoC design guidelines.

nurmi@cs.tut.fi