System on Chip Seminar
SoC or SoP?
A Balanced Approach!
Evan Davidson, IBM
System-on-a-Chip (SoC) has received much publicity during the last few years. It is a goal promulgated by the semiconductor industry that is used to tout the future circuit densities and chip sizes projected by the International Technology Roadmap for Semiconductors (ITRS). The stated ITRS goals represent many challenges for developers some of which have no known solutions. So what happens if the ITRS goals (note: they are not predictions) do not materialize or if they are prohibitively expensive? Is there an alternative? Fortunately there is one; it is called System-on-a-Package (SoP)!
Until recently, most product engineers considered the electronic package as a simple commodity that allowed interconnections for signals and power to chips. In addition, the package was a treated as a mechanical support structure that provided protection and cooling. Given this meager role, the package was considered to be a necessary but not a value-add set of components in most electronic systems. Nowadays and for many reasons, this attitude about electronic packaging is rapidly changing. The incentives for a better outlook for packaging are based upon higher system frequencies, support of more I/O and wiring capacity, better cooling, embedded passives and lower overall packaged electronics (chips plus packages) costs. The summation of all of these attributes is the SoP.
This presentation will straddle the line between chips and packages by discussing prudent tradeoffs. In particular, the performance and cost differences between large chips and small multi-chip modules (MCMs) will be depicted. Furthermore, the significance of the current heavy worldwide investment in organic packaging and its ability to provide superior application solutions at lower prices will be portrayed. The hoped for result will be to engender an increasing respect for the value potential for electronic packages in a world of semiconductors.