System on Chip Seminar
Reconfigurable Computing Architectures and Methodologies for System-on-Chip
Reiner W. Hartenstein, University of Kaiserslautern
Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream. Like microprocessor usage, FPGA programming is RAM-based, but by structural programming (also called "(re)configuration") instead of procedural programming. Now both, host and accelerator are RAM-based and as such also available on the same chip: ready for SoC design.
Now also accelerator definition may be -at least partly- conveyed from vendor site to customer site, such as e. g. for upgrades. A new business model is needed. But this paradigm switch is still ignored: FPGAs do not repeat the RAM-based success story of the software industry. There is not yet a configware industry, since mapping applications onto FPGAs mainly uses hardware synthesis methods, but not really compilation. Supporting only fine-grained reconfigurability of roughly single bit wide configurable logic blocks (CLBs) the mapping tools are mainly based on gate level methods - similar to CAD for hardwired logic.
From a decade of world-wide research on Reconfigurable Computing another breed of reconfigurable platforms is an emerging competitor to FPGAs. In contrast to FPGAs, the Reconfigurable Computing scene uses arrays of c oarse-grained reconfigurable datapath units (rDPUs) with drastically reduced reconfigurability overhead: to directly configure high level parallelism. But the classical machine paradigm does not support soft datapaths because ?instruction fetch? is not done at run time.
To introduce the new business model to cope with the current accelerator design crisis a transition from CAD to compilation is needed, and from hardware/software co-design to configware/software co-compilation. The paper illustrates such a roadmap to reconfigurable computing, supporting the emerging trend to platform-based SoC design.