soc

System on Chip Seminar

A Reconfigurable Communications Processor Architecture

Wolfgang Hoeflich, Chameleon Systems

A new type of reconfigurable communications processor (RCP) architecture was introduced in May 2000 by Chameleon Systems, San Jose, CA. This presentation will introduce the architecture and design flow of the RCP processor and how it relates to the implementation of advanced communications algorithms.

Compared with traditional, fixed DSP architectures, the RCP is a flexible parallel processing architecture. The RCP is aimed at high performance signal processing applications, such as 3G basestations and multi-channel communications applications, for example VoIP and DSL.

This presentation describes the main building blocks of the architecture (Reconfigurable Processing Fabric, programmable interconnects, programmable I/O, RISC processor, Memory Controller, DMA, PCI). System-level features such as the instant reconfiguration will be discussed.

As this architecture requires a new development process, the tool flow into an RCP will be presented. The tool flow involves RTL synthesis, chip P&R, C-code compilation and linking, as well as the verification process using RTL simulation and C debugging tools.

Finally, an applications example, the Turbo Coder, will be shown. The Turbo coders one of the key building blocks used in the IS2000 (UMTS) 3rd generation wireless applications. We will analyze bandwidth, memory and real-estate considerations, as well as the benefits of instant reconfiguration of the RCP. A performance comparison will show the advantages over traditional DSP implementations.


nurmi@cs.tut.fi

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