System on Chip Seminar

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Compiler design for modern embedded processor architectures

Rainer Leupers

Programmable processors are among the major building blocks in today´s embedded SoC designs. In contrast to desktop systems, there is a huge variety of domain specific and even application specific architectures, including microcontrollers, DSPs, NPUs, and ASIPs. The irregular architectures and very high code quality demands of embedded processors create a need for new compiler techniques beyond classical Dragon Book compilation. On one hand, this concerns novel code optimization techniques that take the detailed target architectures into account in order to minimize the overhead of compiled code versus hand-written assembly. On the other hand, retargetable compilers are needed, capable of generating code for flexible architectures, so as to support processor architecture exploration.

This presentation gives an overview of today´s retargetable compiler and code optimization technology for embedded processors. Additionally, new research challenges in the areas of architecture exploration and compilation for recent architecture families like VLIWs and NPUs will be covered.

nurmi@cs.tut.fi