System on Chip Seminar

Galois Field Instruction Set Accelerator in the StarCore SC140 DSP

The capacity of communication channels is improved by forward error correction schemes. In ADSL, the Reed Solomon algorithm is chosen for error detection and correction. It belongs to the family of linear block codes and is based on arithmetics over Galois fields.

Implementing Galois arithmetics on the StarCore SC140 DSP using conventional arithmetics and look-up tables, renders the Reed Solomon algorithm as the bottleneck of the ADSL application.

The solution is to perform Galois field operations on a dedicated hardware element. We chose an instruction set accelerator (ISA). The ISA plug-in module provides a means of enhancing the SC140 instruction set in accordance with the core program flow, using the core control system. This type of acceleration is mainly suitable for enhancing special arithmetic algorithms that their processing is merged with the core?s flow. Thus the overhead of the program control of the module is eliminated without any penalty of its instruction set size. 24 bits of encoding space are dedicated to the ISA instruction set, thus practically there is no limit of the number of operations that can be executed in parallel to the core?s instructions. In addition, there is no need for interrupt based communication protocol between the accelerator and the core, as common in coprocessors.

Galois field algebra is an ideal candidate for this type of accelerator by being a special arithmetic with the need for special operations. About 50 different instructions were defined in the GFISA thus the cycle count could be reduced to its minimum.

The problematic parts of the algorithm on the DSP were identified as polynomial evaluation and MAC (multiply-accumulate) operations over Galois fields and thus implemented in a GFISA (Galois field ISA). The cycle count using the GFISA is reduced by a factor of 20 compared to the cycle count of the SC140.

The idea was proven at high-level. The ISA is expected to consume only few additional silicon area and power.

  SoC 1999

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