System on Chip Seminar

Low-Power DSP Components for Multimedia Communications

Scaled CMOS technologies and growing broadband applications in wired, wireless and fiber media have created many challenges as well as opportunities in communications systems implementations. Digital signal processing technology is an integral part of all communications systems. Reduction of power consumption is one of the major challenges in design of these systems or chips containing 100-500 M transistors.

This talk will address estimation and reduction of power consumption in DSP system implementations. We will begin by describing an approach to estimate power consumption which has been incorporated in the HEAT tool. Then low-power design of arithmetic building blocks (such as binary adders and Montgomery multipliers used in RSA cryptosystems), digital signal processing building blocks (such as digital filters, DCTs, Huffman coders), and error control coding building blocks (such as Turbo coders, low-density parity check codes and Reed-Solomon coders) will be addressed. Use of adaptive filter equalization in optical transmission will be described. At the end, Low-power CAD approaches will be described where power consumption can be reduced by near-optimal scheduling of multiple supply voltages and multiple technology threshold voltages.

  SoC 1999

  SoC 2000

  SoC 2001

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