System on Chip Seminar

Solutions for Communication and Design Reuse in Gigascale Systems-on-Chip

Hannu Tenhunen, Royal Institute of Technology

The future System-on-Chip (SoC) implementations in year 2005 and beyond will be made in technologies with minimum feature size in the range of 0.05 - 0.10 um. The application specific integrated circuits will be up to a billion transistor systems operating at 1 GHz in very demanding self-induced noise conditions. The design is no more a block level problem, but a global communication issue. The key elements in achieving functional silicon with high operating frequency and low power consumption will be the on-chip communications and interconnects. One of the bottlenecks in developing complex circuits is what is called 'the productivity gap'. The designer is not able to design systems-on-chip utilizing the full capacity that the manufacturing technologies can provide. One way to circumvent the situation has been the growing use of Intellectual Property (IP) blocks or Virtual Components (VC) as they are also called. However, more gain in productivity is needed. It is noteworthy that the productivity gain has to be achieved mainly in the digital circuitry domain, since the analog content of SoC designs cannot be grown very much. Here, the functional blocks, processors and memories can be accessed as commercial or legacy VCs. A flexible but efficient interblock communication architecture is what remains on the designer's wish list. The complex systems-on-chip are essentially heterogeneous multiprocessor systems integrated with miniaturized communication networks, bringing up again the importance of communication and synchronization issues. The next step towards SoC integration is to move on to communication platform design and to on-chip heterogeneous multiprocessor based integration platforms.

  SoC 1999

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