System on Chip seminar

System on Chip Seminar

Coarse-grain Reconfigurability for Multimedia SoC

Stamatis Vassiliadis

In embedded system design, we are witnessing a shift towards the utilization of programmable processor cores which are augmented with reconfigurable hardware structures. This shift is even leading to single chip designs which can incorporate both hardwired and reconfigurable hardware. In this light, the MOLEN processor was introduced to achieve this tight integration by only a single one-time architectural extension.

The main idea for the MOLEN processor is to utilize custom configured harware to improve embedded system computing by re-introducing microcode concepts. First, we identify piece(s) of code from an application (set) that when sped up will result in an overall speedup of the application. Subsequently, hardware implementations of such pieces of code are mapped to reconfigurable hardware by writing high-level VHDL code. After synthesis, two types of microcode are generated: reconfiguration microcode (controlling the setting of the reconfigurable hardware) and execution microcode (controlling the execution of the implementation mapped on the reconfigurable hardware). Both types of microcode are referred to as reconfigurable microcode. This approach allows frequently used microcode (by identifying similar microcode across implementations) to be permanently stored on-chip. Furthermore, a storage facility is provided to temporarily store non-frequently used microcode in order to diminish their loading times. In addition, we introduce only two new architectural instructions (set and execute) to point to reconfigurable microcode. I.e., the new instructions do not specify the operation that needs to be performed, instead by executing the reconfigurable microcode the needed setting of and execution on the reconfigurable hardware is being performed. An additional benefit lies in the fact that the set instruction (which initiates reconfiguration microcode) can be scheduled well ahead of the execute instruction (which initiates execution microcode) and thereby hiding the reconfiguration latency of the hardware. The MOLEN approach is generic in the sense that it can support any application (set) and can be utilized to extend any programmable processor family that is augmented with reconfigurable hardware.

This presentation shows the concepts of the MOLEN processor by highlighting an extension of the hardware/software co-design paradigm that utilizes reconfigurable microcode. Furthermore, we present how the MOLEN approach can exploit coarse-grain reconfigurability in order to diminish reconfiguration latencies.

nurmi@cs.tut.fi