System on Chip seminar

System on Chip Seminar

Dynamic reconfigurable systems: blending HW and SW

Diederik Verkest

Embedded, connected systems quickly become part of everyday life. However, migration of traditional multi-media desktop applications to low-power hand-held devices requires a thorough rethinking of the mapping of the application into hardware and software components. Architectures supporting this application domain, should offer flexibility to accommodate new applications (maybe downloaded over the network connection), adapt to changes in the environment, and offer maximal Quality-of-Service (QoS) to the user. Flexibility can be provided by use of software running on embedded processors. Emerging fine-grain and coarse-grain dynamical and partial reconfigurable architectures open the path to dynamic "task" creation in hardware. It is envisaged that these future SoC platforms will consist of tiles containing combinations of application-specific components, various types of instruction-set processors, reconfigurable hardware, and memories, all communicating through an on-chip network. On these platforms various tasks can be created dynamically either in software or hardware and relocated at run-time from software to hardware and back, according to the requested QoS of the various simultaneously running applications.

This presentation will discuss a prototype system demonstrating hardware/software multi-tasking on a platform consisting of a state-of-the-art FPGA (Virtex XC2V6000) connected to a standard microprocessor (StrongARM SA-1110) running Real-Time Linux. Key for enabling this multi-tasking is a packet-switched network that divides the FPGA in a number of isolated tiles in which tasks can be created at run-time. The RTOS manages creation, deletion, and relocation of tasks in software and hardware in a unified manner. Key challenges in this area are identified and some preliminary solutions presented.

nurmi@cs.tut.fi