System on Chip Seminar
November 17-18, 1999, Tampere, Finland
Industry Forum Agenda
Wednesday November 17
| Start Time |
Length (min) |
Company | Title |
|---|---|---|---|
| 10:10 | 20 | Altera | Optimised Filter Design Toools Allow Unprecedented Levels of Performance and Designer Efficiency |
| 10:30 | 20 | Xilinx | - - |
| 10:50 | 20 | LSI Logic | - - |
| 11:10 | 20 | Motorola | - - |
| 11:30 | 20 | STMicroelectronics | - - |
| 11:50 | 20 | Mentor Graphics | HW/SW Coverification with Seamless |
| 12:10 | 20 | Synopsys Finland | - - |
| 12:30 | 25 | Infineon Technologies | Implementation of the EFR vocoder on the Carmel DSP |
| 12:55 | 25 | Analog Devices | The TigerSHARC DSP for 3G Wireless Infrastructure |
| lunch | |||
| 14:15 | 25 | BOPS | - - |
| 14:40 | 20 | Cadence | SoC Design Flow: Part 1. IP Authoring |
| 15:00 | 20 | LSI Logic | - - |
| 15:20 | 20 | Altera | Programmable Logic Tools Support a Simplified Approach to Reed Solomon Design |
| 15:40 | 20 | Synopsys Finland | - - |
Thursday November 18
| Time | Minutes | Company | Title |
|---|---|---|---|
| 09:00 | 20 | BOPS | - - |
| 09:20 | 25 | LSI Logic | - - |
| 09:45 | 20 | Mentor Graphics | VIVACE: Virtual System Prototyping |
| 10:05 | 25 | Motorola | - - |
| 10:30 | 25 | STMicroelectronics | - - |
| 11:00 | 25 | Altera | Design and Simulation of a Viterbi Decoder with Programmable Logic |
| 11:25 | 25 | Synopsys Finland | - - |
| 11:50 | 20 | Analog Devices | GSM Direct Conversion Receiver: The Next Generation Radio |
| 12:10 | 20 | Infineon | Embedded DRAM technology for System ASICs |
| 12:30 | 25 | Cadence | SoC Design Flow: Part 2. System Integration |
| lunch | |||
| 13:40 | 25 | Xilinx | - - |
| 14:05 | 20 | Motorola | - - |
| 14:25 | 20 | Infineon | - - |
| 14:45 | 25 | Mentor Graphics | Embedded Software at Mentor Graphics - towards System on Chip |
| 15:10 | 20 | Cadence | SoC Design Flow: Part 3. System Verification |
| 15:30 | 20 | Analog Devices | DSP Core Design, Analysis and System Simulation: The ADI Architecture Development Environment |
| 16:00 | 20 | STMicroelectronics | - - |
| 16:20 | 20 | BOPS | - - |
| 16:40 | 20 | Xilinx | - - |
nurmi@cs.tut.fi