soc

International Symposium on System-on-Chip 2006

Tampere Hall, Tampere, Finland, November 13-16, 2006

SoC 1999

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SoC 2001

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SoC 2003

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NOC Symposium

Programme in a Glance

You can also take a look at the detailed Preliminary Schedule.

The registration is now open.

Total 9 INVITED TALKS, 20 contributed talks in 6 SESSIONS, 19 posters in 2 sessions, 8 industry presentations.

Theme of the year: "SoC Design Flow and Methodology."

MONDAY Nov. 13 Tutorial on Bluespec System Verilog 09:00 - 17:00

TUESDAY Nov. 14

  • 09:00 - 10:00 Registration and coffee
  • 10:00 - 10:30 Opening
  • 10:30 - 11:15 THE FUTURE OF NANOMETER SOC DESIGN (Steve Leibson, Tensilica)
  • 11:15 - 12:15 Industry1 (Sonics, Recore) and coffee
  • 12:15 - 13:00 SYSTEM LEVEL DESIGN EXPERIENCES AND THE NEED FOR STANDARDIZATION (Vesa Lahtinen, Nokia)
  • 13:00 - 14:20 Lunch
  • 14:20 - 15:40 SESSION: SoC Applications
  • 15:40 - 16:40 Industry2 (Infineon, Mentor Graphics) and coffee
  • 16:40 - 17:25 BLUESPEC SYSTEM VERILOG (Arvind, MIT)
  • 17:25 - 19:00 Reception

WEDNESDAY Nov. 15

  • 09:00 - 10:00 SESSION: Reconfigurability
  • 10:00 - 11:00 Industry3 (Synplicity, Arteris) and coffee
  • 11:00 - 11:45 DESIGN METHODOLOGY AND ARCHITECTURE FOR SDR SYSTEMS (John Glossner, Sandbridge Technologies)
  • 11:45 - 12:45 SESSION: TTA and Networks
  • 12:45 - 13:45 Lunch
  • 13:45 - 14:30 CO-MODEL FOR CO-DESIGN : FROM UML TO SYSTEMC USING MDA TECHNOLOGIES (Jean-Luc Dekeyser, LIFL)
  • 14:30 - 15:30 Industry4 (Target, Evatronix) and coffee
  • 15:30 - 16:15 TESTABILITY OF SOC DESIGNS (Yervant Zorian, Virage Logic)
  • 16:15 - 17:00 VIRTUAL HARDWARE PLATFORMS IN ESL DESIGN (Andreas Hoffmann, CoWare)
  • 17:00 - 17:15 Coffee break
  • 17:15 - 18:30 PANEL: The Verification Gap: Will it ever close?
  • 19:00 - 22:00 Banquet

THURSDAY Nov. 16

  • 09:00 - 09:45 EXPLORING APPLICATION-LEVEL CONCURRENCY IN SOC DESIGN (Leandro Soares Indrusiak, TU Darmstadt)
  • 09:45 - 11:00 Poster1 (9 posters) and coffee
  • 11:00 - 12:20 SESSION: Network-on-Chip
  • 12:20 - 13:30 Lunch
  • 13:30 - 14:15 DATAFLOW TRANSFORMATIONS IN HIGH-LEVEL DSP SYSTEM DESIGN (Shuvra Bhattacharyya, U Maryland)
  • 14:15 - 15:15 Poster2 (10 posters) and coffee
  • 15:15 - 16:35 SESSION: SoC Design and Analysis
  • 16:35 - 16:50 Short break
  • 16:50 - 17:30 SESSION: MPSoC Issues
  • 17:30 - 17:40 Closing
  • 18:30 - 21:00 Ice-hockey Tappara-Ilves
  • 21:00 - 23:00 Dinner