System on Chip Seminar

SoC 1999

SoC 2000

SoC 2001

SoC 2002

Links

SoC Modeling Design and Validation

Location: Tampere University of Technology, Korkeakoulunkatu, Tampere
Room: To be informed later
Lecturer: Prof. Ahmed Jerraya

This course is provided free of charge, but pre-registration is required. TUT students can acquire 1 cu from the course.

Agenda

08:45   Opening the course
    1 - Introduction to SoC design
        - Definition, examples, challenges, classical design
          approaches, requirements
    2 - HW-SW Architecture for SoC
        - Components: HW and SW Computation modules, Memories
        - Communication schemes
        - Organization schemes
        - Programming Models
10:45   Coffee break
11:00
    3 - SoC Modeling and Validation
        - Basic Concepts
        - HW and SW Components Modeling, Models of Computation,
          Abstraction levels
        - Interconnect Modeling, Communication Abstraction
        - Languages
        - Execution models for Heterogeneous Models, Cosimulation
13:00   Lunch
14:00
    4 - Design Methods and tools for SoC
        - Models and Steps
        - Architecture Exploration
        - Component Integration
    5 - Advanced issues
     	- SW Modeling, OS abstraction
      	- Test and Debug for SoC
        - Final Discussion
16:00   End of course