System on Chip Seminar
Program
Wednesday, November 17
09:30 - 10:00 Registration and coffee
10:00 - 10:10 Opening of the seminar (Jari Nurmi)
10:10 - 10:30 Keynote speech by Jarmo Takala, TUT
10:30 - 11:15 Jan Rabaey, University of California, Berkeley:
11:30 - 12:15 Design Technologies for Heterogeneous Architectures, Pleiades
12:30 - 13:15 Ravi Subramanian, MorphICs, Inc.: Reconfigurable Digital
Communication Systems On A Chip
13:15 - 14:15 Lunch
14:15 - 15:00 Heinrich Meyr, Aachen Technical University: Modeling of
Embedded Processors with LISA for Architecture Exploration
and System-Level Simulation
15:15 - 16:00 Stefan Pees, Aachen Technical University: Modeling of
Embedded Processors with LISA for Architecture Exploration
and System-Level Simulation (part II)
16:00 - 16:15 Coffee break
16:15 - 17:30 Panel discussion: The Biggest Challenges in System-on-Chip
Integration
Panelists: Jan Rabaey, Heinrich Meyr, Ravi Subramanian, Vojin Zivojnovic,
Oz Levia
19:00 - 21:00 Dinner
Thursday, November 18
09:00 - 09:45 Vojin Zivojnovic, AXYS Design Automation GmbH:
10:00 - 10:45 Cycle and Phase Accurate DSP Modeling and Integration for HW/SW
Co-Verification of SoC
10:45 - 11:00 Coffee break
11:00 - 11:45 Oz Levia, Improv Systems, Inc.:
12:00 - 12:45 From Application Specifications in Java to System in Silicon
using Programmable System Architecture (PSA)
12:45 - 14:00 Lunch
14:00 - 14:45 Naji Ghazal, University of California, Berkeley: Retargetable
Performance Estimation using Parameterized Processor
Architecture Model
15:00 - 15:45 Henk Corporaal, Delft Technical University:
Transport Triggered Architectures (TTA)
15:45 - 16:00 Coffee break
16:00 - 16:45 Henk Corporaal continues
16:45 - 17:00 Seminar wrap-up
17:30 - 21:00 Optional post-seminar event
nurmi@cs.tut.fi