International Symposium on System-on-Chip 2006
13.11.2006 - 16.11.2006
Tampere Hall
Tampere-Finland
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SOC 2006 International Symposium on System-on-Chip 2006 13.11.2006 - 16.11.2006 Tampere Hall Tampere-Finland |
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MONDAY |
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SESSION MonTut: Tutorial on Bluespec System Verilog Date: 13 November 2006 Time: 09:00 - 17:00 Location: Sonaatti |
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SESSION MonReg: Registration Date: Monday November 13, 2006 Time: 17:00 - 17:30 Location: in front of Sonaatti |
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TUESDAY |
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SESSION TueReg: Registration and Coffee Date: Tuesday November 14, 2006 Time: 09:00 - 10:00 Location: In front of Studio Sponsor(s): Tensilica |
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SESSION TueAmOR1: Opening Date: Tuesday November 14, 2006 Time: 10:00 - 10:30 Location: Studio |
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SESSION TueAm2: Invited1 Date: 14 November 2006 Time: 10:30 - 11:15 Location: Studio Chair: Jari Nurmi, Tampere University of Technology |
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| 10:30 |
[1084] - THE FUTURE OF NANOMETER SOC DESIGN Steve Leibson, Tensilica, USA |
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SESSION TueAm3: Industry1 and Coffee Date: 14 November 2006 Time: 11:15 - 12:15 Location: Rondo |
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| 11:15 |
[1075] - USING SPIRIT CORES IN SONICSSTUDIO Kamil Synek, Sonics, Inc., United States |
| 11:45 |
[1074] - IP REUSE FOR FLEXIBLE & EFFICIENT DSP PLATFORM CHIPS Paul Heysters, Recore Systems, Netherlands |
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SESSION TueAm4: Invited2 Date: 14 November 2006 Time: 12:15 - 13:00 Location: Studio Chair: Jari Nurmi, Tampere University of Technology |
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| 12:15 |
[1079] - SYSTEM LEVEL DESIGN EXPERIENCES AND THE NEED FOR STANDARDIZATION Vesa Lahtinen, Nokia, Finland |
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SESSION TueLunch: Lunch Date: 14 November 2006 Time: 13:00 - 14:20 Location: Restaurant Fuuga |
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SESSION TuePm1: SoC Applications Date: 14 November 2006 Time: 14:20 - 15:40 Location: Studio |
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| 14:20 |
[1011] - AN ULTRA LOW-POWER BODY SENSOR NETWORK CONTROL PROCESSOR WITH CENTRALIZED NODE CONTROL Sungdae Choi, Kyomin Sohn, Hyejung Kim, Jooyoung Kim, Seong-Jun Song, Namjun Cho, Jerald Yoo, Hoi-Jun Yoo, KAIST, South Korea |
| 14:40 |
[1036] - IMPLEMENTATION OF AN HSDPA RECEIVER WITH A CUSTOMIZED VECTOR PROCESSOR Kim Rounioja, Kimmo Puusaari, Nokia, Finland |
| 15:00 |
[1058] - A LEAK RESISTANT SOC TO COUNTERACT SIDE CHANNEL ATTACKS Daniel Mesquita, LIRMM, France; Benoit Badrignans, Netheos, France; Lionel Torres, Gilles Sassatelli, Michel Robert, LIRMM, France; Fernando Moraes, PUCRS, Brazil |
| 15:20 |
[1060] - ANALOG TELEVISION, WIMAX AND DVB-H ON THE SAME SOC PLATFORM Daniel Iancu, Sandbridge Technologies, United States |
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SESSION TuePm2: Industry2 and Coffee Date: 14 November 2006 Time: 15:40 - 16:40 Location: Rondo |
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| 15:40 |
[1076] - DEVELOPMENT AND VERIFICATION OF EMBEDDED FIRMWARE USING VIRTUAL SYSTEM PROTOTYPING Thomas Eckart, Infineon Technologies AG, Germany; Martin Schnieringer, VaST Systems Technologies, Germany |
| 16:10 |
[1089] - ESL - A VIABLE APPROACH? Mark Croft, Mentor Graphics, USA |
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SESSION TuePm3: Invited3 Date: 14 November 2006 Time: 16:40 - 17:25 Location: Studio Chair: Jari Nurmi, Tampere University of Technology |
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| 16:40 |
[1083] - BLUESPEC SYSTEM VERILOG Arvind, Massachusetts Institute of Technology, USA |
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SESSION TuePm4: Reception in Rondo Date: 14 November 2006 Time: 17:25 - 19:00 Location: Rondo |
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WEDNESDAY |
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SESSION WedAm1: Reconfigurability Date: 15 November 2006 Time: 09:00 - 10:00 Location: Studio |
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| 09:00 |
[1002] - DYNAMIC RECONFIGURATION: CORE RELOCATION VIA PARTIAL BITSTREAMS FILTERING WITH MINIMAL OVERHEAD Ferrandi Fabrizio, Massimo Morandi, Marco Novati, Marco Santambrogio, Donatella Sciuto, Politecnico di Milano, Italy |
| 09:20 |
[1050] - EXTERNAL MEMORY CONTROLLER FOR VIRTEX II PRO Blagomir Donchev, Technical University - Sofia, Bulgaria; Georgi Kuzmanov, Georgi Gaydadjiev, Delft University of Technology, Netherlands |
| 09:40 |
[1061] - RECONFIGURABLE FABRIC INTERCONNECTS Stamatis Vassiliadis, Ioannis Sourdis, TU Delft, Netherlands |
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SESSION WedAm2: Industry3 and Coffee Date: 15 November 2006 Time: 10:00 - 11:00 Location: Rondo |
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| 10:00 |
[1072] - CONVERGENCE OF SIMULATION AND IN-SYSTEM DEBUG Doug Amos, Synplicity, United Kingdom |
| 10:30 |
[1087] - ARTERIS' NETWORK-ON-CHIP (NOC) POWER MANAGEMENT; A NEW SCALE CONTROLLING SOC ENERGY Alain Fanet, Arteris, France |
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SESSION WedAm3: Invited4 Date: 15 November 2006 Time: 11:00 - 11:45 Location: Studio |
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| 11:00 |
[1081] - DESIGN METHODOLOGY AND ARCHITECTURE FOR SDR SYSTEMS John Glossner, Sandbridge Technologies, USA |
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SESSION WedAm4: TTA and Networks Date: 15 November 2006 Time: 11:45 - 12:45 Location: Studio |
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| 11:45 |
[1043] - LOOP SCHEDULING FOR TRANSPORT TRIGGERED ARCHITECTURE PROCESSORS Perttu Salmela, Risto Mäkinen, Pekka Jääskeläinen, Jarmo Takala, Tampere University of Technology, Finland |
| 12:05 |
[1051] - MINIMIZING HOT SPOTS IN NOCS THROUGH A DYNAMIC ROUTING ALGORITHM BASED ON INPUT AND OUTPUT SELECTIONS Masoud Daneshtalab, Ali Afzali-Kusha, Siamak Mohammadi Tehran university, Iran |
| 12:25 |
[1059] - EFFICIENT LINK ARCHITECTURE FOR ON-CHIP SERIAL LINKS AND NETWORKS Jayaprakash Balachandran, IMEC, Belgium |
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SESSION WedLunch: Lunch Date: 15 November 2006 Time: 12:45 - 13:45 Location: Restaurant Fuuga |
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SESSION WedPm1: Invited5 Date: 15 November 2006 Time: 13:45 - 14:30 Location: Studio |
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| 13:45 |
[1082] - CO-MODEL FOR CO-DESIGN : MODELING, SIMULATION AND PERFORMANCE ANALYSIS Jean-Luc de Keyser, LIFL, France |
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SESSION WedPm2: Industry4 and Coffee Date: 15 November 2006 Time: 14:30 - 15:30 Location: Rondo |
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| 14:30 |
[1088] - DESIGN OF ASIPS IN MULTIPROCESSOR SOCS USING THE CHESS/CHECKERS RETARGETABLE TOOL SUITE Gert Goossens, Dirk Lanneer, Werner Geurts, Johan van Praet, Target Compiler Technologies, Belgium |
| 15:00 |
[1077] - ENHANCED LEGACY 68000 INSTRUCTION SET ARCHITECTURE AS A BASIS FOR SYSTEM ON CHIP DEVELOPMENT Wojciech Sakowski, Silesian University of Technology, Poland; Wlodzimierz Wrona, Akademia Techniczno-Humanistyczna, Poland; Sebastian Kaprowski, Maciej Przybysz, Evatronix SA, Poland |
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SESSION WedPm3: Invited6 Date: 15 November 2006 Time: 15:30 - 16:15 Location: Studio |
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| 15:30 |
[1080] - TESTABILITY OF SOC DESIGNS Yervant Zorian, Virage Logic, USA |
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SESSION WedPm4: Invited 7 Date: 15 November 2006 Time: 16:15 - 17:00 Location: Studio |
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| 16:15 |
[1085] - VIRTUAL HARDWARE PLATFORMS IN ESL DESIGN Andreas Hoffmann, CoWare, USA |
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SESSION WedPm5: Coffee break in front of Studio Date: 15 November 2006 Time: 17:00 - 17:15 Location: Studio |
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SESSION WedPm6: Panel discussion Date: 15 November 2006 Time: 17:15 - 18:30 Location: Studio |
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SESSION WedDinner: Banquet in downtown Tampere Date: 15 November 2006 Time: 19:00 - 22:00 Location: Restaurant |
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THURSDAY |
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SESSION ThuAm1: Invited8 Date: 16 November 2006 Time: 09:00 - 09:45 Location: Studio |
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| 09:00 |
[1086] - EXPLORING APPLICATION-LEVEL CONCURRENCY IN SOC DESIGN Leandro Soares Indrusiak, Darmstadt University of Technology, Germany |
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SESSION ThuAm2: Poster1 and Coffee Date: 16 November 2006 Time: 09:45 - 11:00 Location: Rondo |
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[1027] - POWER ESTIMATION FOR IP-BASED MODULES Yaseer A. Durrani, Teresa Riesgo, Universidad Politecnica de Madrid, Spain |
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[1032] - SERIAL BUS ENCODING FOR LOW POWER APPLICATION Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi, University of Tehran, Iran |
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[1034] - OPTIMIZED SYNTHESIS OF DSP CORES COMBINING LOGIC-BASED AND EMBEDDED FPGA RESOURCES Gabriel Caffarena, Juan A. Lopez, Carlos Carreras, Octavio Nieto-Taladriz, Universidad Politecnica de Madrid, Spain |
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[1039] - FAULT-TOLERANT ROUTING APPROACH FOR RECONFIGURABLE NETWORKS-ON-CHIP Pekka Rantala, Teijo Lehtonen, Jouni Isoaho, Juha Plosila, University of Turku, Dept. of Information Technology, Communication Systems Lab., Finland |
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[1040] - ALGORITHMS FOR LEAKAGE REDUCTION WITH DUAL THRESHOLD DESIGN TECHNIQUES Konrad Engel, Thomas Kalinowski, Roger Labahn, Frank Sill, Dirk Timmermnn, University of Rostock, Germany |
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[1013] - REALIZING MULTIOPERATIONS FOR STEP CACHED MP-SOCS Martti Forsell, VTT, Finland |
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[1019] - USING CONSTRAINT PROGRAMMING TO ACHIEVE OPTIMAL PREFETCH SCHEDULING FOR DEPENDENT TASKS ON RUN-TIME RECONFIGURABLE DEVICES Yang Qu, Juha-Pekka Soininen, Technical Research Centre of Finland (VTT), Finland; Jari Nurmi, Tampere University of Technology, Finland |
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[1020] - DESIGN AND VERIFICATION OF A VHDL MODEL OF A FLOATING-POINT UNIT FOR A RISC MICROPROCESSOR Claudio Brunelli, Jari Nurmi, Tampere University of Technology, Finland |
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[1022] - INTERCONNECTION GENERATION FOR SYSTEM-ON-CHIP DESIGN Markus Winter, Gerhard Fettweis, TU Dresden, Vodafone Chair Mobile Communications Systems, Germany |
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[1056] - PARAMETERIZING SIMULATED ANNEALING FOR DISTRIBUTING TASK GRAPHS ON MULTIPROCESSOR SOCS Heikki Orsila, Tero Kangas, Erno Salminen, Timo Hämäläinen, Tampere University of Technology, Finland |
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SESSION ThuAm3: Network-on-Chip Date: 16 November 2006 Time: 11:00 - 12:20 Location: Studio |
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| 11:00 |
[1017] - EVALUATION OF CURRENT QOS MECHANISMS IN NETWORKS ON CHIP Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes, Pontificia Universidade Catolica do Rio Grande do Sul, Brazil |
| 11:20 |
[1025] - MINIMISING DYNAMIC POWER CONSUMPTION IN ON-CHIP NETWORKS Robert Mullins, University of Cambridge, United Kingdom |
| 11:40 |
[1044] - COMPARISON OF A TIMING-ERROR TOLERANT SCHEME WITH A TRADITIONAL RE-TRANSMISSION MECHANISM FOR NETWORKS ON CHIPS Srinivasan Murali, Stanford University, United States; Rutuparna Tamhankar, Marvell Semiconductors, United States; Federico Angiolini, Antonio Pullini, University of Bologna, Italy; David Atienza, EPFL, Switzerland; Luca Benini, University of Bologna, Italy; Giovanni De Micheli, EPFL, Switzerland |
| 12:00 |
[1047] - A HIGH-THROUGHPUT NETWORK-ON-CHIP ARCHITECTURE FOR SYSTEMS-ON-CHIP INTERCONNECT Abdelhafid Bouhraoua, Muhammad ElRabaa, KFUPM, Saudi Arabia |
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SESSION ThuLunch: Lunch Date: 16 November 2006 Time: 12:20 - 13:30 Location: Restaurant Fuuga |
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SESSION ThuPm1: Invited9 Date: 16 November 2006 Time: 13:30 - 14:15 Location: Studio |
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| 13:30 |
[1078] - DATAFLOW TRANSFORMATIONS IN HIGH-LEVEL DSP SYSTEM DESIGN Sankalita Saha, Sebastian Puthenpurayil, Shuvra Bhattacharyya, University of Maryland, USA |
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SESSION ThuPm2: Poster2 and Coffee Date: 16 November 2006 Time: 14:15 - 15:15 Location: Rondo |
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[1041] - REGISTER FILE PARTITIONING WITH CONSTRAINT PROGRAMMING Perttu Salmela, Tampere University of Technology, Finland; Chung-Ching Shen, Shuvra S. Bhattacharyya, University of Maryland, College Park, United States; Jarmo Takala, Tampere University of Technology, Finland |
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[1046] - FORMAL MODELLING OF MULTICLOCKED SOC SYSTEMS Tomi Westerlund, Juha Plosila, University of Turku, Finland |
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[1048] - HIGH-LEVEL OPTIMIZATION OF ASYNCHRONOUS SYSTEMS UTILIZING CONDITIONAL RESTRUCTURING Mahtab Niknahad, Kamran Saleh, Mehrdad Najibi, Hossein Pedram, Amirkabir University of Technology, Iran |
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[1049] - STRUCTURAL VERIFICATION IN MINIMAL TIME Martin Holzer, Bastian Knerr, Markus Rupp, TU-Vienna, Austria |
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[1063] - SIXD: A CONFIGURABLE APPLICATION-SPECIFIC SISD/SIMD MICROPROCESSOR SOFT-CORE Nehir Sönmez, Arda Yurdakul, Bogazici University, Turkey |
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[1066] - A VALIDATION AND PERFORMANCE EVALUATION TOOL FOR PROTONOC David Castells-Rufas, Jaume Joven, Jordi Carrabina, Cephis - UAB, Spain |
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[1068] - ANALYSIS OF CROSSTALK AND PROCESS VARIATIONS EFFECTS ON ON-CHIP INTERCONNECTS Ethiopia Nigussie, Sampo Tuuna, Juha Plosila, Jouni Isoaho, University of Turku, Finland |
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[1070] - NON-POWER-OF-TWO FFTS: EXPLORING THE FLEXIBILITY OF THE MONTIUM Pascal T. Wolkotte, Marcel D. van de Burgwal, Gerard J. M. Smit, University of Twente, The Netherlands |
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[1071] - PROGRAMMABILITY IN DICTIONARY-BASED COMPRESSION Jari Heikkinen, Jarmo Takala, Tampere University of Technology, |
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SESSION ThuPm3: SoC Design and Analysis Date: 16 November 2006 Time: 15:15 - 16:35 Location: Studio |
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| 15:15 |
[1024] - APPLICATION SCENARIOS IN STREAMING-ORIENTED EMBEDDED SYSTEM DESIGN Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal, Technical University of Eindhoven, Netherlands |
| 15:35 |
[1042] - HARDWARE COST ANALYSIS FOR WEAKLY PROGRAMMABLE PROCESSOR ARRAYS Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Juergen Teich, University of Erlangen-Nuremberg, Germany |
| 15:55 |
[1055] - A COOPERATIVE, ACCURATE SOLVING FRAMEWORK FOR OPTIMAL ALLOCATION, SCHEDULING AND FREQUENCY SELECTION ON ENERGY-EFFICIENT MPSOCS gioia pari, Martino Ruggiero, alessio guerri, luca benini, michela milano, University of Bologna - DEIS, Italy; davide bertozzi, University of Ferrara, Italy; Alexandru Andrei, ESLAB, Department of Computer and Info Science, Sweden |
| 16:15 |
[1057] - MODELING AND PERFORMANCE ANALYSIS OF GALS ARCHITECTURES Sohini Dasgupta, Alex Yakovlev, University of Newcastle, United Kingdom |
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SESSION ThuPm3b: Short break Date: 15 November 2006 Time: 16:35 - 16:50 Location: Studio |
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SESSION ThuPm4: MPSoC Issues Date: 16 November 2006 Time: 16:50 - 17:30 Location: Studio |
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| 16:50 |
[1007] - THE IMPACT OF COMMUNICATION ON THE SCALABILITY OF THE DATA-PARALLEL VIDEO ENCODER ON MPSOC Erno Salminen, Tero Kangas, Timo D. Hämäläinen, TUT, Finland |
| 17:10 |
[1038] - FAST MULTI-DIMENSION MULTI-CHOICE KNAPSACK HEURISTIC FOR MP-SOC RUN-TIME MANAGEMENT Chantal Ykman-Couvreur, IMEC, Belgium |
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SESSION ThuPm5: Closing Date: 16 November 2006 Time: 17:30 - 17:40 Location: Studio |
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SESSION ThuHockey: Ice Hockey Tappara vs. Ilves Date: 16 November 2006 Time: 18:30 - 21:00 Location: Hakametsä Ice Hall Sponsor(s): Mentor Graphics |
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SESSION ThuDinner: Goodbye supper in Restaurant Plevna Date: 16 November 2006 Time: 21:00 - 23:00 Location: Restaurant |
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