soc

System on Chip Seminar


SoC 1999

SoC 2000

SoC 2001

SoC 2002

SoC 2003


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Enabling Technologies for System-on-Chip Development

November 20-21, 2002, Tampere, Finland

Registration is closed!

Panel discussion summary


Organized by

Tampere University of Technology
Institute of Digital and Computer Systems

SoC-Mobinet project co-funded by the European Commission

TELESOC graduate school


Main Sponsor

NOKIA


Pre-seminar course

Pre-seminar course on SoC Modeling Design and Validation will be held at TUT on Nov. 19, 2002.


Speakers

Preliminary program


Venue

The event takes place in Tampere Hall, Yliopistonkatu 55


Exhibition

There is an exhibition of SoC design and implementation technology providers. Potential exhibitors are requested to contact directly prof. Nurmi.

List of exhibitors
  • Altera
  • AXYS
  • Cadence Design Systems
  • Celoxica
  • LISAtek
  • Mentor Graphics
  • Nordic VLSI
  • PACT
  • QuickSilver Technology
  • Synopsys
  • Tensilica
  • Xilinx

Preliminary exhibition floorplan


Dinner

The seminar banquet will take place in the Palace of Finlayson at Kuninkaankatu 1.


Post-seminar event

The post-seminar event is a dinner at restaurant Plevna provided in cooperation with Mentor Graphics.


SoC 2002 Bus Transportation
Tuesday Nov. 19

08:15 Tampere-Pirkkala airport
08:45 TUT

08:15 Hotel Ilves
08:45 TUT

16:15 (after the course) TUT
16:45 Hotel Ilves

Wednesday Nov. 20

08:15 Tampere-Pirkkala airport
08:45 Hotel Ilves
09:00 Hotel Ilves
09:05 railway station
09:10 Tampere Hall

09:30 Hotel Ilves
09:40 Tampere Hall

09:10 Tampere-Pirkkala airport
09:40 Tampere Hall

18:40 Tampere Hall
18:50 Hotel Ilves
19:00 Finlayson Palace

18:45 Tampere Hall
19:00 Finlayson Palace

Thursday Nov. 21

08:30 Hotel Ilves
08:50 Tampere Hall

17:15 Tampere Hall
17:25 railway station
17:35 Plevna

17:15 Tampere Hall
17:25 Hotel Ilves
17:35 Plevna