ATM chips and products

Mika Lepistö


About this document

This document has been produced in the Telecommunications Laboratory at Tampere University of Technology (TUT). It is based on technical data and preview information sent by vendors listed in Chapter 3. Chapters 1 and 2 describes the characteristics of products represented by those vendors. In Chapter 4 you can find reference list.

This document can be found at:

Table of Contents

1. AAL and ATM Layers

1.1. Brooktree Corporation

Bt8220, ATM Receiver/Transmitter

The Bt8220 provides DS1, E1, DS3, and E3 physical layer convergence procedure (PLCP) functions and provides for the generation and checking of AAL 1/3/4/5 formatted ATM payloads. The host system can transfer data cells through a dedicated FIFO input/output port in conjunction with the Bt8215 Bidirectional Cell FIFO. The Bt8220 will direct up to four different virtual channel/paths, with a maskable screen, to different I/O ports [2].

Picture 1. Bt8220 ATM Receiver/Transmitter.

Bt8222, ATM Receiver/Transmitter w/UTOPIA

The Bt8222 is a software compatible upgrade to the Bt8220. The host UTOPIA interface provides four cells of internal buffer capability with an optional low latency mode. The high speed serial interfaces use differential PECL voltage levels [2].

Picture 2. Bt8222 ATM Receiver/Transmitter w/UTOPIA.

Bt8215, Bidirectional Cell Buffer

The Bt8215 provides full duplex communication between 32-bit system or processor buses and 8-bit I/O peripherals. The Bt8215 is intended for use in applications such as ATM and SMDS cell buffering, HDLC buffering, and cell switching [2].

Picture 3. Bt8215 Bidirectional Cell Buffer Block Diagram.

Bt8215EVM, Evaluation Module

The 8215 EVM implements an 8-port ATM Switch Fabric. The switch provides up to 622 Mbit/s of total bandwidth. Header translation is performed in software. The board connects to either the Bt8215 EVM-CB or the Bt8220 EVM to generate cell traffic. The source code for the header translation is available under a license agreement [2].

Bt8222EVM, Evaluation Module

The Bt8222EVM allows the user to evaluate the performance of the Bt8222 ATM Receiver/Transmitter, the Bt8215 Bidirectional cell FIFO, and the Bt8330 HDLC formatter in an ATM CSU/DSU application. The Bt8222EVM also may be used to generate user defined ATM cell or DXI frame traffic, or to capture incoming traffic for test and evaluation purposes [2].

1.2. Fujitsu Microelectronics Inc.

ATM EISA Evaluation Board

This card demonstrates the capabilities of Fujitsu`s ATM devices. All of the adaptation, ATM and Physical layer functions are handled autonomously by the Fujitsu chips. The card uses on board packet memory to buffer data during segmentation and reassembly and provides support for the SONET over Multimode Fiber physical interface directly on the card [5].

Picture 4. ALC/NTC Based Adaptor Card.

MB86680 SRE, ATM Switch Element

The SRE is a 4x4 cell-switch building-block, which has buffered outputs and selectable high and low priority queues [6].

MB86687 ALC, Adaptation Layer Controller

The ALC provides a complete implementations both AAL3/4 and AAL5 procedures. User data is transferred to and from system memory via an on-chip high-speed DMA controller which can interface to a variety of 32- and 64-bit bus structures.The ALC is a full-bidirectional device and can support up to 1024 simultaneous connections in both receive and transmit directions at network speeds up to 155 Mbit/s [6].

MB86689 ATC, Address Translation Controller

The ATC performs real-time translation of ATM header information for serial rates up to 155 Mbit/s. It can supply a routing tag up to 3 bytes long that is used to determine the destination for each cell [6].

Picture 5. ATM-LAN.

1.3. Integrated Telecom Technology (IgT)

WAC-020-A, AAL5 SAR Processor

This processor translates packet-based data into 53-byte ATM cells using ATM Adaptation Layer 5 cell segmentation and reassembly (SAR) [11].

Picture 6. Typical WAC-020-A System Block Diagram.

WAC-021-A, AAL1 SAR Processor

The processor provides DS1/DS3 line interface access to an AAL1 Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of configuration, the user data, and the statistics. It provides a microprocessor interface for configuration, management, and statistics gathering. It provides SAR of eight 2 Mbit/s data streams or one 45 Mbit/s data stream [12].

Circuit Interface Features

Transmit Interface Features

Receive Interface Features

Statistics Features

TST-ATM, Version 1.3 ATM Test System

The ATM Test System can be used sending and receiving ATM cells over a SONET or DS3 physical layer (in future releases, more physical layer interfaces).

In the transmit direction, the ATM Test System converts PC files to ATM cells, sends the ATM cells, maps the ATM cells into the proper interface payload, and generates any desired alarms and errors. In the receive direction, the ATM Test System detects alarms, counts errors, captures and counts cells based on several capture options. It has a 512-cell buffer to compare incoming data in real time for long-term testing.

The ATM Test System consist of a control unit, an interface module, and a Windows-based software package. This graphical user interface provides configure test, full test results and cell counts [14].

ATM Features

SONET Features

WAC-185-A, ATM Cell Multiplexer

The WAC-185-A connects four ATM layer or physical layer UTOPIA Level 1 devices to a single ATM layer UTOPIA Level 1 device. On the receive side, it generates four read enable signals to the input devices and accepts four cell available signals from the input devices. On the transmit side, it generates four write enable signals for the output devices and accepts four cell available signals from the output devices. The transmit side accepts a priority and port destination from the ATM layer, and places the cell in the appropriate queue. The queues are maintained in an external 16-bit wide RAM using a linked list with head and tail pointers [15].

WAC-186-A, ATM UPC/OAM Processor

This processor checks incoming connections for violations of negotiated traffic parameters, and performs hardware-intensive processing of OAM cells [16].

WAC-187-A, ATM Routing Table

WAC-188-A, ATM Switch Element

Each switch element device has 1.2 Gbit/s throughput and can be joined together in large switch fabrics to create very high bandwidth switching systems [18].

1.4. LSI Logic Corporation

ATMizer Chip Family

The single-chip solution integrates all ATM layer functions, the segmentation and reassembly sublayer, and a subset of the transmission convergence sublayer [26].

Picture 7. ATMizer Block Diagram.

BD-ATMizer R/T-BRD, ATMizer R/T Evaluation Board

The board incorporates a 50 MHz ATMizer Chip, 128 kbytes of 12 ns, zero-wait-state memory and 128 kbytes of 35 ns memory for the secondary port, 512 kbytes of host memory, jumper programmable for latency and dual serial ports. PROM resident code included on the board supports bootup, download and debug capabilities [25].

BD-ATMizer R/T-EK, ATMizer Evaluation Kit

In addition to the Evaluation Board, this includes the PROM Monitor and the AAL5 SAR sources [25].

BD-ATMizer R/T-SDP, ATMizer System Development Platform

This includes two ATMizer R/T Evaluation Boards, one configuration as the host, the other as the ATM engine. It provides a platform to emulate an ATM network. Two of these platforms with framer modules provide a complete point-to-point ATM network environment (includes PROM Monitor and AAL5 SAR sources) [25].

Picture 8. Block diagram of ATMizer R/T Platform.

SW-ATMizer R/T-PMON, PROM Monitor Source Code

This is 95% written in C. The Prom Monitor provides bootup, download and debug capabilities. It includes drivers for the serial ports, initialization code and other C library functions [25].

SW-ATMizer R/T-AAL5, AAL5 SAR Code

This is a optimized assembly code [25].

1.5. MAZ Microelektronik Anwendungszentrum Hamburg GmbH

ATM-Modules DAS 500 ATM Switch

Specific ATM products can be configured from several DAS 50x modules.

The Switch Module consisting of one or more switch elements has the following main functions:

The Control Unit Module includes following functions:

The Network Adapter Modules mainly offers the following functions:

The Translator Module maps internal and external VPI/VCI addresses to each other and either serves for coupling of the ATM switch to an external one or a public or private ATM network.

The Line Terminator (LT) Module is used for coupling of remote ATM systems by use of optical fibres as transmission medium [27].

1.6. SuperNet Networking Ltd.


SuperX provides AAL 5 and ATM layers functionality and has a built in ATM switching capability. The device has three data ports; Link port, Host port and a Bus Interconnect port. Link port provides an interface to ATM physical layer devices. Host port provides a DMA interface to an external packet memory and access to SuperX status and control registers. The Bus Interconnect port (X_Port) is a 32 bit I/O port that provides a high throughput interconnect among multiple SuperX devices. This port is used for the construction of an ATM switch [52].

Picture 9. SuperX block diagram.

1.7. Temic

29C70, ATM Adaptation Layer Controller for AAL 3/4 and AAL5

The 29C70 implements CCITT recommendation I.363 and is designed to interface to ATM Network with the maximum speed of 155 Mbit/s. A general control unit provides a full chip control with a microprocessor interface. The device provides also errors metering and internal loop capabilities for testing purposes. The 29C70 has a maximum system clock speed of 25 MHz. The 29C70 has a programmable AAL number so that up to 24 AAL controllers can be connected on the same ATM Layer Bus. It detects errors such as CRC, Tempo, Overflow and Sequencing. The CPCS-PDU shall be checked by the processor (CPI, BETAG, length for AAL 3/4, CPCS Trailer, CPI, length for AAL5) [53].

Picture 10. 29C70 functional block diagram.

1.8. TransSwitch Corporation

SARA Chipset

The two-chip SARA chipset provides an interface between packet-oriented equipment and ATM networks. SARA provides segmentation and reassembly functions in compliance with both the T1S1.5 ATM Adaptation Layer Type 3/4 and Type 5, including the CPCS and the SAR. Most overhead functions associated with conversion to and from cells are provided. This includes packet queuing, buffer management and DMA, CRC generation and checking, and those ATM network-specific functions required to segment and reassemble cells over the attached network link.

SARA supports up to a maximum of 65536 virtual circuits. Up to 8191 virtual circuits may have packets queued for segmentation, with and equal number being concurrently reassembled. A throughput rate of at least 150 Mbit/s in each direction may be achieved [54].

Picture 11. Typical ATM Network Interface Unit Implementation.

CellBus Logical Operation

CellBus is designed as a versatile and low-cost logical and electrical structure for implementation of a variety of ATM cell-based products. CellBus is both a backplane interconnect and an on-card inter-device interconnect technology. CellBus does not specify the physical implementation. The basic CellBus is structured as a number of CellBus Bus User units interconnected by a common synchronous bus. ATM cells are transferred, via the CellBus, from any Bus User to any other Bus User, or to any number of other Bus Users (multicast) [58].

CDB Device, Cell Delineation Block


The CDB is an ATM cell interface device. The CDB function is to extract ATM cell from, and insert ATM cells into, a line interface signal having one of several possible transmission formats. Cell delineation is performed by means of a Header Error Control (HEC) byte search. Cell rate adaptation is also performed by generating and terminating unassigned ATM cells of a specified format [59].

Picture 12. CDB Device.

2. Physical Layer

2.1. Applied Micro Circuits Corporation

S3005/S3006, SONET/SDH OC-3/12 Transmitter and Receiver

The S3005/S3006 Synchronous Electrical Transmit Interface, SETI, and Synchronous Electrical Receive Interface, SERI, SONET/SDH and E4 transmitter and receiver chips are fully integrated serialization/deserialization interface devices covering E4 (139.264 Mbit/s), SONET OC-3 (155.52 Mbit/s) and SONET OC-12 (622.08 Mbit/s). The chipset performs all necessary serial-to-paraller and paraller-to-serial functions in conformance with SONET/SDH and E4 transmission standards.

The chipset can be used with 19.44, 38.88, 51.84, and 77.76 MHz reference clocks when operated in the SONET/SDH OC-3 or OC-12 modes [1].

S3011/S3012, SONET/SDH/ATM OC3 Transmitter and Receiver

These chips are fully integrated serialization/deserialization SONET OC-3 (155.52 Mbit/s) interface devices. The S3012 performs SONET/SDH frame detection [1].

S3014, SONET/SDH Clock Synthesis/Clock Recovery Unit

The function of this unit is to derive high speed timing signals for SONET/SDH-based equipment.

In Clock Recovery mode, the S3014 receives either an STS-3/STM-1 (155.52 Mbit/s) or STS-12/STM-4 (622.08 Mbit/s) scrambled NRZ signal and recovers the clock from the data. In Clock Synthesis mode, the S3014 receives a 19.44, 51.84, or 155.52 MHz reference clock and outputs an STS-3/STM-1 or STS-12/STM-4 differential ECL clock [1].

S3015/S3016, E4/STM-1/OC-3 Interface Circuits

The S3015 transmitter and S3016 receiver derive high speed timing signals for SONET/SDH or PDH-based equipment. The chipset can be used with a 19.44 MHz reference clock when operated in the SONET/SDH OC-3 mode and 17.408 MHz clock in E4 mode. On-chip coded-mark-inversion (CMI) encoding and decoding is provided for 139.264 Mbit/s and 155.52 Mbit/s interfaces [1].

S3017/S3018, SONET/SDH/ATM OC-12 Transmitter and Receiver

These chips are fully integrated serialization/deserialization SONET OC-12 (622.08 Mbit/s) interface devices. Can be used with a 19.44 or 77.76 MHz reference clock [1].

S6003, S3014 Evaluation Board

This board allows demonstration of AMCC`s S3014 SONET clock synthesis and recovery unit [1].

S6004, S3005/S3006 Evaluation Board

The S6004 allows demonstration of AMCC`s S3005 and S3006 SONET/SDH OC-3/12 transmitter/receiver chipset [1].

2.2. Cypress Semiconductor

CY7B951 SST, SONET/SDH Serial Transceiver

The SONET/SDH Serial Transceiver (SST) is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52 MHz or 51.84 MHz NRZ or NRZI serial data stream and to provide differential data buffering for the transmit side of the system [3].

CY7B923 & CY7B933, HOTLink Transmitter/Receiver

The HOTlinks are point-to-point communications building blocks that transfer data over high-speed serial links (fiber, coax, and twisted pair) at 160 to 330 Mbit/s [4].

2.3. Fujitsu Microelectronics Inc.

MB86683 NTC, Network Termination Controller

The NTC is a full duplex network terminator, which supports multiple interface types. It implements all Transmission Convergence (TC) sub-layer functions for physical media based on SDH/SONET, DS3 and E3 [6].

2.4. Integrated Telecom Technology (IgT)

WAC-011-A, ATM DXI HDLC Controller

The controller operates at any rate up to 52 Mbit/s, and is suited for X.25, frame relay, SMDS DXI, and ATM DXI applications. HDLC level 2 functions are implemented inside the device [7].

WAC-012-A, 622 Mbit/s SONET ATM UNI Processor

The processor maps 53-byte ATM cells asynchronously into a synchronous SONET/SDH payload and operates at the STS-12c/STM-4 rate (622 Mbit/s). It transfers ATM data through a 16-bit FIFO interface and SONET/SDH-formatted data through a synchronous 8-bit interface [8].

WAC-013-B, 51/155 Mbit/s SONET ATM UNI Processor

The processor maps 53-byte ATM cells asynchronously into a synchronous SONET/SDH payload and operates at the STS-3c/STM-1 rate (155.52 Mbit/s), and the STS-1 rates (51.84 Mbit/s, 25.92 Mbit/s, 12.96 Mbit/s). It transfers ATM data through a 8-bit FIFO interface and SONET/SDH-formatted data through a synchronous 8-bit interface [9].

MOD-013-B, 51/155 Mbit/s SONET ATM UNI Processor Module

This module uses WAC-013-B processor to map ATM cells and provides access to the SONET/SDH interface via an optical interface. The module has a built-in SONET crystal, an Analog Devices clock recovery circuit, and an optical

transceiver. It is made for fast prototyping and low-volume ATM interface production [10].

WAC-034-A, PDH ATM UNI Processor

This processor maps ATM-cells into a synchronous DS3, E3, or E4 payload. This device can also be used with external circuitry in any application requiring a DS1 or E1 interface [13].

TAC-011-B, B3ZS Encoder/Decoder

The B3ZS (Bipolar with 3-zero Substitution) encoder/decoder is for use in either STS-1 or DS3 interfaces. Compatible with CMOS and TTL signals [19].

TAC-030-A, DS3 Framer

This DS3 Framer performs all DS3 overhead processing for use in wide-band data transport applications and provides complete support for C-bit framing [20].

EAC-011-C, HDB3 Encoder/Decoder

This High Density Bipolar 3 encoder/decoder is for use in CEPT E1, E2 and E3 interfaces [21].

EAC-013-A, E13 Multiplexer

The E13 Multiplexer performs E1-to-E2 and/or E2-to-E3 multiplexing/demultiplexing simultaneously and independently. It provides complete support for E2 framing, and is ideally suited for equipment requiring E1-to-E2-toE3 connection [22].

EAC-030-A, E3 Framer

This device performs all E3 overhead processing for use in wide-band data transport applications [23].

SAC-013-A, Async DS3-to-SONET Mapper

The SAC-013-A provides all DS3 desynchronization, DS3 mapping, and SONET Path Overhead termination for use in hybrid Wide-band data transport applications. The SAC-013-A STS-1 interface can be used for direct connection to line overhead terminators, and allows for multiplexing to higher-level STS-N rates [24].

2.5. PMC Sierra Inc.

PM1501 EVMB, Evaluation Motherboard

The PM1510 EVMB is a generic processor core for use with a family of evaluation boards designed to facilitate test, evaluation, and demonstration of PMC devices.

The EVMB provides processing capability and communication capability between itself and a daughterboard containing the PMC device to be evaluated. It is based on a 68HC11 microcontroller, which contains 8K bytes of ROM that implements the kernel for the FORTH operating system and language [28].

PM4341A T1XC, T1 Framer Transceiver

The T1XC is software configurable, allowing feature selection without changes to external wiring [29].

PM4541 T1XC EVBD, T1XC Evaluation Daughterboard

This board allows for the test, evaluation, and demonstration of the PMC PM4341 T1XC device. It is also compatible with the PM6341 E1XC device. This board can be used standalone with up to two T1XC devices but has been especially designed to mate with the PMC PM1501 EVMB to form a complete evaluation system [30].

PM5312 STTX, SONET/SDH Transporting Transceiver

The device processes the transport overhead of STS-1, STS-3/STM-1, and STS-12/STM-4 streams and optionally provides byte interleaved multiplexing of lower rate streams. The STTX operates with the PM5318 SIPO 622 Mbit/s SONET/SDH Serial to Paraller / Paraller to Serial Converter to implement SONET/SDH compliant line interfaces [31].

PM5318 SIPO, SONET/SDH Serial to Paraller/Paraller to Serial Converter 622 Mbit/s

The SIPO is a fully integrated high speed SONET/SDH compatible 8:1 and 1:8 mux/demux. It is used at speeds of 622 and 155 Mbit/s [32].

PM5343 STXC, SONET/SDH Transport Overhead Transceiver

This device processes the transport overhead (section overhead) of STS-1, and STS-3/STM-1 streams at 51.84 Mbit/s and 155.52 Mbit/s. The STXC transmits/receives SONET/SDH frames via a bit serial or byte serial interface and formats/processes section and line overhead [33].

PM5344 SPTX, SONET/SDH Path Terminating Transceiver

The SPTX implements payload alignment and path termination for three STS-1 (AU3) paths or a single STS-3c (AU4) path, mapping these payloads onto a Telecombus-like system backplane. The SPTX operates in conjunction with the PM5343 STXC to form a complete system for terminating section, line, and path overhead [34].

PM5345 SUNI, Saturn User Network Interface 155.52 Mbit/s

Implements the ATM transmission convergence (TC) sublayer for Broadband ISDN. Operates at 19.44 Mbytes/s, processing a duplex 8-bit or 16-bit data stream and mapping ATM cells into a SONET STS-3c or SDH STM-1 compatible bit serial stream operating at 155 Mbit/s [35].

PM5346 SUNI-LITE, Saturn User Network Interface 51.84 & 155.52 Mbit/s

Implements the SONET/SDH processing and ATM mapping functions of a 155 Mbit/s, or 51 Mbit/s ATM User Network Interface. The SUNI/LITE receives SONET&SDH frames via a bit serial interface, recovers clock and data, and processes section, line, and path overhead. It performs framing (A1, A2), descrambling, detects alarm conditions, and monitor section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. The SUNI-LITE frames to the ATM payload using cell delineation. HCS error correction is provided.

The SUNI-LITE transmits SONET/SDH frames via a bit serial interface and formats section, line, and path overhead appropriately. It performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) [36].

PM5347 SUNI, SUNI-155-Plus Saturn User Network Interface

Implements the ATM transmission convergence (TC) sublayer for ATM using the SONET/SDH 155.52, 51.52, 25.92 and 12.96 Mbit/s. Includes on-chip clock recovery and clock synthesis at all rates. Supports Unshielded Twisted Pair, Shielded Twisted Pair and fiber optic interfaces [37].

PM5355 SUNI-622, 622Mbit/s Saturn ATM User-Network Interface

Implements the ATM transmission convergence (TC) sublayer for ATM using the SONET/SDH 622.08, 155.52 and 51.84 Mbit/s [38].

PM5361 TUPP, SONET/SDH Tributary Unit Payload Processor

The TUPP is a monolithic integrated circuit that implements a configurable, multi-channel, payload processor for alignment of SONET virtual tributaries (VTs) or SDH tributary units (TUs). The TUPP is configurable to process any legal mix of tributaries. The TUPP operates in conjunction with the PM5323 TSPP and the PM5344 SPTX to align tributaries such that they can be switched by the PM5371 TUDX [39].

PM5371 TUDX, SONET/SDH Tributary Unit Cross Connect

The TUDX allows non-blocking switching of tributaries within two SONET STS-3 or SDH STM-1 streams. Programmable idle code can be inserted into any channel. The TUDX is cascadable in a systolic or bused manner and provides programmable control outputs that are useful in constructing larger switching arrays. The TUDX is configured, controlled and monitored via a generic 8-bit microprocessor bus interface [40].

PM6341 E1XC, E1 Framer/Transceiver

The PM6341 E1XC is a device suitable for use in many E1 systems (such as CSU, DSU, CH BANK, MUX, DPBX, DACS, and ESDX) with a minimum of external circuitry. The E1XC is software configurable [41].

PM7321 PLPP, ATM Physical Layer Protocol Processor

The PMC PM7321 PLPP is a SMDS/ATM physical layer processor with an integrated DS3 framer. PLCP sublayer DS1, DS3, E1 and E3 processing is supported as is ATM cell delineation. It is used to implement ATM wide area user network interfaces (UNI) and network node interfaces (NNI) [42].

PM7321 T3XC, T3 Framer/Transceiver

The PM7321 T3XC provides a receive and transmit M23 or C-bit parity framing interface in accordance with ANSI standards. Provides integral HDLC support for the path maintenance data link used in the C-bit parity application [43].

PM7345 SUNI-PDH, Saturn User-Network Interface for ATM Plesiochronous Digital Hierarchy

The PM7345 SUNI-PDH is an ATM physical layer processor with integrated DS3 and E3 framing. PLCP sublayer DS1, DS3, E1, and E3 processing is supported as is ATM cell delineation. When configured for DS3, the SUNI-PDH accepts and outputs either a B3ZS-encoded bipolar or a unipolar signal compatible with M23 and C-bit parity applications. When configured for E3 transmission system sublayer processing, it accepts and outputs either HDB3-encoded bipolar or a unipolar signal compatible with G.751 and G.832 applications. When configured for DS1, or E1, it accepts and outputs a unipolar signal with appropriate clock and frame pulse signals for physical sublayer processing. When configured for other transmission systems, it provides a generic interface for physical sublayer processing [44].

PM7521 PLPP EVBD, PLPP Evaluation Daughterboard

This board (with PM1501 EVMB) allows for the test and evaluation of the PMC PM7321 PLPP device. The PLPP EVBD supports three transmission system formats: DS1, DS3, and external. The DS1 format utilizes the PMC PM4341 T1XC T1 framer and transceiver. The DS3 format utilizes the internal PLPP T3 framer and the external Silicon Systems SSI78P236 DS3 LIU [45].

PM8313 D3MX, M13 Multiplexer/Demultiplexer

Integral framer supports the M23 or C-bit parity DS3 formats with path maintenance data link processing and bit oriented code support for FEAC channel termination. Supports either the M12 or the G.747 formats to allow DS1 or E1 signals to be multiplexed into a DS3 signal [46].

PM8513 D3MX EVBD, D3MX Evaluation Daughterboard

This board allows for the test, evaluation, and demonstration of the PMC PM8313 D3MX and PMC PM4312 DDSX devices. This board has been specially designed to mate with the PMC PM1501 EVMB to form a complete evaluation system [47].

SCI-PHY, Saturn Compliant Interface For ATM PHY Devices

This is PMC-Sierra's recommended interface protocol for the interconnect of physical layer (PHY) ATM devices to ATM layer or ATM Adaptation Layer processors. It has been developed with the cooperation of the Saturn ATM chip development group to cover all application bit rates up to 622 Mbit/s and to handle both ATM layer to single-PHY and ATM layer to multi-PHY connections. The SCI-PHY is a superset of the Utopia specification. Within SCI-PHY, multi-PHY operation and data parity support are required [48].

2.6. Raytheon Semiconductor

RCC700, Fibre Channel/ESCON/ATM/SSA Transceiver

The RCC700 is a transmitter/receiver IC integrating a complete phase-locked loop clock recovery and data retiming/regeneration subsystem, a phase-locked loop clock synthesizer, a 10:1 mux, a 1:10 demux, an 8-bit/10-bit encoder/decoder. RCC700-200 can be used for the transport of ATM LAN operating at 194.4 Mbaud (155.52 Mbit/s OC-3 data rate with 8-bit/10-bit overhead) [49].

2.7. Siemens

V23806-A84-C1, Single Mode ATM Transceiver

The transceiver operates at 155.52 Mbit/s [50].

Low Cost ATM/SONET OC-3 Transceiver

The transceiver operates at 155.52 Mbit/s [51].

2.8. TransSwitch Corporation

ALI-25C and ALI-25T, ATM Line Interface Devices for 25 Mbit/s Operation

TXC-07025 Chip Set

The ATM Line Interface 25 Mbit/s (ALI-25) Chip Set provides the complete ATM-25 Physical Layer function including the Transmission Convergence (TC) and Physical Media Dependent (PMD) sub-layers and operates over existing cable plants (STP, UTP-3,4,5) up to 100 meters. This chip connects to available ATM-layer protocol chips such as the SARA-S and the SARA-R (TXC-05501 and 05601) of FIFO designs [55].

SOT-3 Device, STM-1/STS-3/STS-3c Overhead Terminator


The SOT-3 is programmable device which performs section, line and path overhead processing for STM-1/STS-3/STS-3c signals [56].

SYN155C Device, 155 Mbit/s Synchronizer, Clock & Data Output


The SYN155C synchronizer device provides a complete STS-3/STM-1 frame synchronization function in a single low-power CMOS unit. It supports two frame synchronization modes: a full tracking mode which finds frame and verifies it on following frames; and a non-tracking mode which finds frame but performs no verification [57].

2.9. Valor Electronics Inc.

Cougar Series FL6033 & SF6035

A complete filter module for interface to 100Base-Tx, TP/PMD (FDDI over copper) and 155 Mbit/s ATM transceiver chips [60].

Cougar Series PT6024 & ST6021/23/25

A complete transformer and common mode choke interface for 100Base-TX, TP/PMD (FDDI over copper) and 155 Mbit/s ATM applications [61].

3. Vendors

3.1. Applied Micro Circuits Corporation

6195 Lusk Boulevard

San Diego, CA 92121, USA

Phone: (619) 450 9333

Fax: (619) 450 9885

3.2. Brooktree Corporation

9868 Scranton Road

San Diego, CA 92121-3707, USA

Phone: (619) 452-7580

Fax: (619) 452-1249

Comodo Oy

Rälssintie 6

00720 Hki

Phone: (90) 351 5100

Fax: (90) 351 5355

3.3. Cypress Semiconductor Corporation

3901 North First Street

San Jose, CA 95134, USA

Phone: (408) 943 2600


ScandComp Finland Oy

Asemakuja 2 C

02770 Espoo

3.4. Fujitsu Microelectronics Inc.

3545 North First Street, San Jose

CA 95134 1804,USA

Phone: (408) 922 9000

Fax: (408) 432 9044

Sales Office:

Fujitsu Microelectronics, Ltd.

Kung Hans Väg 12

S-191 76 Sollentuna, Sweden

Phone: 08-6266720

Fax: 08-6266711

3.5. Integrated Telecom Technology (IgT)

18310 Montgomery Village Avenue

Suite 300, Gathersburg MD 20879, USA

Phone: (301) 990 9890

Fax: (301) 990 9893


Optotel AS.

Skovlytoften 4

Box 124, 2840 Holte, Danmark

Phone: +45-45-41 05 06

Fax: +45-42-42 07 30

3.6. LSI Logic Corporation

1551 McCarthy Boulevard, Milpitas

CA 95035, USA

Phone: (408) 433 2801

Fax: (408) 433 1561

Email(Mr. Michael Barar, Technical Manager):

3.7. MAZ Microelektronik Anwendungszentrum Hamburg GmbH

Karnapp 20, D-21079 Hamburg, Germany

Phone: +49 40 76629 1623

Fax: +41 40 76629 199

3.8. PMC Sierra Inc.

8501 Commerce Court, Burnaby, BC

Canada, V5A 4N3

Phone: (604) 668 7300

Fax: (604) 668 7301

3.9. Raytheon Semiconductor

350 Ellis Street, Montain View

CA 94043 7016, USA

Phone: (800) 722 7074

Fax.: (415) 966 7742



Kehäkuja 6, 05460 Hyvinkää

Phone:+358-14-434 600

Fax:+358-14-434 609

3.10. Siemens


Farnell Electronic Services

Työpajakatu 5, PL 25, 00581 Hki

Phone: +358-0-739 100

Fax: +358-0-70 15 639

3.11. SuperNet Networking Ltd.

16, Totzeret Ha`aretz Street

Tel-Aviv 67891, Israel

Phone: 972-3-6969632

Fax: 972-3-6963554


3.12. Temic


Farnell Electronic Services

Työpajakatu 5, PL 25, 00581 Hki

Phone: +358-0-739 100

Fax: +358-0-70 15 639

3.13. TransSwitch Corporation

8 Progress Drive, Shelton

CT 06484, USA

Phone: (203) 929 8810

Fax: (203) 926 9453

3.14. Valor Electronics Inc.

9715 Business Park Avenue, San Diego

CA 92131, USA

Phone: (619) 537 2500

Fax: (619) 537 2525