System-on-Chip is the ultimate level of integration, attempting to capture complete electronic systems on a single die. The driving forces for such development are improvements regarding all relevant aspects of consumer electronics: price, size, features and power consumption.
The challenges of System-on-Chip integration raise from circuit complexity gradually increasing to billions of transistors. The design productivity needs to grow, implying a paradigm shift in design reuse and abstraction. Also, the design focus is changing from circuit block functionality to interblock communications on the gigascale chips. One obstacle for efficient use of silicon is the increasing power density which calls for improved low-power techniques on every level of design hierarchy.
This research group addresses the SoC design especially in the context of digital signal processing and communications. Architecture development of systems and processors is carried out. Raise of reuse from block level to reusable integration platforms and on-chip communication architectures is one of the key targets. Essentially, the future systems on chip are embedded multiprocessor systems where the communication architecture sets or removes the limits of the system capabilities. Also, the low-power low-voltage issues are addressed down to the logic and transistor levels, even down to processing technology in the form of piloting and early adopting of new promising technologies.
Contacts: jari dot nurmi at tut dot fi
See also project descriptions. (not much of use, badly out of date)