(slightly out of date...)
The following projects have funding application pending or are under preparation.
Application pending at TEKES. 2003-2006. Co-investigator.
Application pending at Academy of Finland. 2003-2006.
Application pending at Academy of Finland. 2003-2006.
2001-2004. Funding by EU and companies. Link to SoC-Mobinet homepage.
The objective of this proposal is to provide a European research and educational centre to enhance the number of electronic engineers holding System-on-Chip skills required for mobile Internet applications. This proposal outlines a strategy and key building elements for a European research and education programme in System-on-Chip focused on mobile Internet. The programme will be based on recognised centres of excellence with a tight coupling of education, research and leading industrial manufacturers of wireless systems.
The activities will be twofold: firstly initiating joint R&D projects aimed at developing new classes of devices required for the mobile Internet with special focus on methods of making the design flow more efficient, and secondly provisioning of a European Centre of Excellence for training in socware for mobile Internet applications.
Both activities will be organised and run in close co-operation with European industrial players in the mobile Internet market either directly involved in the consortium or contributing financially through a so called SoC-MOBI-Club.
The industrial users of SoC-MOBINET are all strongly involved in telecommunication and wireless systems which form the basis for the future mobile Internet applications. The project will be open for other users from the mobile Internet area.
The objective of the System-on-Chip (SoC) initiative is to create a European centre aimed at driving the future of electronic design. It represents a unique collaboration involving the Commission, industry and academia to create a world-leading centre for the electronic and related design industries of the future.
A European SoC training centre will offer access to a comprehensive range of research and development facilities, covering fully-serviced laboratories, methods, tools and employee training support. The initiative will develop the centre into a leading world location for System-on-Chip design. Working in partnership with Europe's top universities in this field (KTH, TUT, DTU, UTU and CTI) and a range of private sector partners, the vision can become reality.
The purpose of the research activity is to support the education program in full breath and not to produce an integrated demonstrator or gadget. SoC-MOBINET's output is therefore people and competence in the SoC area. For the same reason the exploitation plan is measured via recruitment of the individuals as well as integration of the research results in the courses and cross-fertilisation of course content due to exchange work between universities and between academia and industry.
2002-2005. Funding by Nordic Industry Fund and companies. Link to SoC-SME homepage.
SOC-SME is a Northern Europe network in the field of SoC/ASIC/FPGA/embedded systems. The primary target is to facilitate the take-up of System-on-Chip integration technologies and technologies leading towards System-on-Chip, especially in small and medium-size enterprises. Interested companies and service and training providers are welcome to join the network. The network spans the Nordic and Baltic countries.
2001-2004. Two parallel projects, one funded by the Academy of Finland, the other by TEKES and companies. Link to COMPLAIN homepage.
The project aims at identifying a new architecture for flexible and configurable module-to-module communication between multiple on-chip processors and shared/distributed memory in the electrically harsh environment of low-voltage high-speed circuits. The architecture shall be scalable to the extent of the gigatransistor scale complexity.
This project is specifically tackling two major areas: Asynchronous on-chip communication and performance analysis of on-chip multiprocessor networks. The communication issues include research on scalable communication methods in integrated embedded multiprocessor environment, development of protocol-based synchronization and arbitration methods, studies of globally asynchronous - locally synchronous IP-based architectures, Network-on-chip (NOC) approach to communications, and probabilistic communication schemes. The performance analysis concentrates on further development of multiprocessor and distributed systems performance analysis methods to be able to analyze integrated embedded multiprocessor-type of integration platforms, and on extraction of traffic profiles or traffic models for the analysis of integration platforms. The profiles are tying the research to practical applications in the area of telecommunication systems.
2002-2005. Participating in this project funded by TEKES and companies as a co-investigator. Headed by Prof. Jarmo Takala.
1999-2002. Funding by TEKES and companies.
Power consumption has become one of the most important parameters in digital circuit design, besides chip area and performance. The power consumption can be addressed on various levels from system level through architecture to logic and transistor level design and fabrication technology. This project tackles the power issues mostly on technology and circuit levels, but is reaching at architectural optimizations as well in the search for low power.
One of the approaches in the project is to use SOI (Silicon on Insulator) process to achieve lower parasitic capacitance levels. A complete DSP processor prototype circuit is used as a vehicle in comparing the power-performance characteristics of SOI vs. CMOS in a real case. On the circuit level, the attention is turned towards low-voltage operation. Due to the quadratic dependence between the supply voltage and power consumption, the use of as low a voltage as possible is aimed at. Different logic styles are studied in terms of operation at low voltages. The third level of optimization consists of architectural improvements in DSP processors for low-power operation. One of the key issues in embedded DSP core environments is the program memory utilization. The project targets at reduced access frequencies and also at smaller memory footprint by developing new instruction coding/decoding schemes. The key idea is to develop application-specific encoding schemes to minimize the entropy of instructions and instruction sequences.
2000-2002. Funding by the Academy of Finland.
Application specific integrated circuits beyond year 2005 will be up to a billion transistor systems operating at 1 GHz in very demanding self-induced noise conditions. The key elements in achieving functional silicon with high operating frequency and low power consumption will be the on-chip communications and interconnects. In this project, the issue is addressed by researching new protocols, implementation architectures and circuitry feasible to enable realization of the future interconnect requirements. This includes robustness, synchronization issues, error correction coding, noise immunity, low power and high-speed operation for on-chip module to module communication.
1999-2001. Funding by TEKES and companies.
System-on-Chip (SoC) can be defined to be an integrated system containing application specific logic and programmable processors along with their software, where the majority of the functionality stems from the integrated software. As the capacity of integrated circuits will reach the billion transistor milestone within a few years we will face new problems in the design of such circuits. One solution to keep pace with the increasing capacity is the use of virtual components and on-chip buses to increase productivity. These are currently studied in REVIVAL project. The project addresses both the design of virtual components for reuse and the use of VCs and buses to build a SoC. Especially the verification of integrated systems containing several buses is focused on. The applications are in different types of wireless and wireline communication systems.
2000. TEKES funding.
The project aims at identifying a new architecture for flexible and configurable module-to-module communication between multiple on-chip processors and shared/distributed memory in the electrically harsh environment of low-voltage high-speed circuits. The architecture shall be scalable to the extent of the gigatransistor scale complexity. This is a prestudy which has produced two project proposals under the same title, one for the Academy of Finland and another for TEKES.
1999-2002.
Research on architectures and system modelling of GPS. No further details available.
1998-2001.
Research on System-on-Chip architectures for CDMA receivers. No further details available.
1998-1999. Funded by TEKES and companies.
The general goal was to improve the practical reuse of Application Specific Integrated Circuit (ASIC) design elements. This was seen as one of the most efficient ways to fight the “productivity gap”, which means that the designer cannot keep pace with the rapid development of integrated circuit capacity and cannot fully exploit it using traditional design methods.
The project was carried out in four Work Packages (WPs), each with their own focus:
1993-1994.
The design cost and the complexity of ASICs in DSP applications are increased continuously. The design efficiency in these large systems is not sufficient enough. Also in the IC world the lack of standards defined at the macro level are obvious, which has forced every vendor to create their own macros. Although there are today some new tools and methods to increase the total productivity of the designer, we have to still face the fact that even the best and the most expensive tools have their limitations in the pressure of ever growing demands. Application specific signal processing library elements such as parametrizable digital filters and processor cores are starting to gain a lot of interest in several companies throughout the world. These are the main reasons why TUT started this R&D project in 1993.
During the DSP macro research project a compact basic function library was determined to help the design of larger macro function components and to increase the abstraction level of design. Second objective was that the existing design environment will be completed by developing the model of the structures, which are not supported properly by current tools. With these macro models the design environment independence will be used to guarantee the use of efficient commercial tools with the models and to make it possible to use several tools together. During the project, the researchers have found out efficient description styles for synthesis to provide application specific optimization yielding fast and efficient VLSI implementation. The main objectives were to determine the development methodology of the library to facilitate the model development, to decrease the time needed for documentation, to clarify documents, to speed up the verification of designs, to facilitate the reuse of designs, and to rationalize design methods. Other goals were to improve the quality of designs by moving emphasizes from VLSI to DSP (more efficient algorithms and architectures), at the same time allowing more careful high level analysis to find out the right specification for products, and to improve the DSP and synthesizable VHDL knowledge in the companies. The final goal was to develop design systems by utilizing existing standards and thus facilitating the evaluation of VHDL into ASIC design in the companies.
The project was a part of the ASPI (Application Specific Circuit Design) project of the national ESV (Electronics Design and Manufacturing Technologies) program.
The funding was by Technology Development Center (TEKES), Nokia Mobile Phones, Nokia Cellular Systems, Nokia Data Communications, Nokia Research Center (Espoo and Tampere), and Fincitec Oy.
1993-1994.
This project (KOMPLEKS) was a part of ESV (Electronics design and manufacturing technologies) technology programme which was started at year 1991. General objective of the project was to find out (EDA) methods for the verification of system specification, requirements for transition from system level specification to hardware/software design and to develop hardware system simulation on the PCB level.
The research was focused on system simulation methods, different high level model libraries, how system simulation affects design productivity and quality, system bus modeling and VHDL usability in system level modeling. Because a part of simulation and verification tasks requires quite a lot of computing resources and data handling capabilities, also methods for parallel processing in a workstation network have been developed in the project.
KOMPLEKS was financed by TEKES, Nokia Research Center, ABB Corporate Research, Kone Elevators, Nokia Cellular Systems and Mariachi.
1992-1994.
The sampling rate demands for digital signal processing systems are getting to very high frequencies in many applications. In this project, asynchronous self-timed VLSI design methods have been promoted. The advantage of self-timed cirucits is the data-driven synchronization of the operation. High speed can be achieved without any clock skew problems, and the circuit automatically enters a low-power mode when data is not fed in. The system is also completely scalable to arrays of circuits with minor speed penalty, since the synchronization is local. The project, ending in 1994, produced a fully asynchronous FIR filter processor circuit as a demonstrator of the techniques. In another branch of the project, a signal processor implementation of a hybrid DCT codec was developed using TMS 320C40 signal processors. KONTRA was financed by TEKES, VLSI Solution Oy, Nokia Research Center, Benefon Oy and TH-Electronics Oy.
1994.
Self-timed VLSI implementations of DSP systems. The project started in 1994 as a spin-off from the KONTRA project. NASKALI was funded by TEKES, Nokia Mobile Phones, Nokia Data Communications, VLSI Solution Oy, and Benefon Oy.
1990-1993.
A speech coding oriented ASDSP architecture and its full custom VLSI implementation were developed in project, jointly with AMS, Austria and VLSI Solution Oy. The project was completed in 1993. High data throughput and low power operation have been achieved with a powerful instruction set, allowing the use of a relatively low clock frequency (13 MHz). The instructions of the processor are all single cycle. Moreover, several instructions, packed in one 42-bit instruction word, can be executed in parallel. For zero-overhead looping there is a hardware loop counter. Another specific feature is the simplified data addressing. Also a low-power stand-by mode has been achieved by freezing the internal clock when there is no active program.
1994.
Logarithmically encoded signals are common in many areas of signal acquisition, communication, and signal processing. In digital signal processing, logarithmic encoding offers interesting advantages also from the implementation point of view. The primary advantage is that multiplication is transformed to addition of logarithms. This is significant because most signal processing algorithms use multiplications extensively, and those are costly to implement in hardware in the traditional fashion. Furthermore, some operations constantly avoided in signal processing algorithms for their complexity, such as division, square root and squaring, become extremely simple subtractions or shifts of logarithms. On the other hand, addition/subtraction of logarithmic numbers needs more hardware than in the linear domain. In this project, the development and silicon implementation of a digital signal processor for processing logarithmically encoded data was carried out. The architecture and efficient hardware implementation were in the scope of this project. The project started at the end of 1993, and was funded by the Ministry of Education under the Finnish neo-industrialization program.
Contacts: jari dot nurmi at tut dot fi
See also the general group description.